Integrated circuits, such as, for example, complex programmable logic devices (CPLD) comprise a large number and variety of programmable circuits. By selectively choosing which of the circuits on the CPLD are used and how the circuits are interconnected, a CPLD may be used to implement a wide range of custom circuit designs. Devices such as CPLDs have one or more arrays (e.g., configuration blocks) of memory cells (e.g., configuration bits) that configure the CPLD's functionality. Each of the memory cells (configuration bits) has an address which may be specified by a word-line and a bit-line. The configuration blocks are programmed at start-up by storing values into the configuration bits. The addresses of the configuration bits must also be determined for simulation. Due to the large number of configuration cells, the process of programming the configuration bits may be complex and problematic for complex PLDs.
In one conventional method, the memory cells (configuration bits) and their associated word-lines and bit-lines are identified manually, and the result would be specific to only one simulator. A separate computer program is written for each programmable logic device circuit design. Therefore, great care must be taken to avoid computer programming errors when using this cumbersome and tedious conventional method. Furthermore, each time the programmable logic device circuit design is changed, the program which identifies the memory cells and their associated word-lines and bit-lines must be changed, by once again manually identifying the wordline and bitline addresses of the configuration bits. Configuration bit errors due to manual entry mistakes may appear as circuit errors, thereby adding to the complexity and difficulty of circuit simulation.
Some conventional methods load the configuration bits into the CPLD serially. Therefore, the program which loads the configuration bits into the CPLD must know the correct order. As there may be over 1 million configuration bits, manually generating the order may be time consuming and error prone.
As the complexity of devices such as CPLDs increases, the number of memory cells (configuration bits) increases. Consequently, the risk of error increases when using a conventional manual method for address determination. Furthermore, as separate programs need to be written for each programmable logic device design change, the time spent programming increases dramatically. Clearly, this could delay getting a new product to market and increase design and test costs.